In some communication systems, a frequency divider produces a lower frequency from an input signal. In one application, for example, a frequency divider is part of a phase-locked loop (PLL), which generates an RF clock signal of a desired frequency utilizing a voltage controlled oscillator (VCO). The RF clock signal is input to the frequency divider, which produces a lower frequency signal. The lower frequency signal is input to a phase-frequency detector along with a reference signal. A charge pump is controlled by the outputs of the phase-frequency detector. The charge pump output is connected to a loop filter to control the frequency of the VCO such that the phase and frequency of the lower frequency signal matches that of the reference signal. This results in an RF clock signal that is higher frequency but still phase-locked to the reference signal.
The reference signal may have a lower frequency than the VCO output signal. The PLL may use a frequency divider so that the VCO output signal frequency is a multiple of the reference signal frequency. Digital logic may control the frequency divider to allow it to divide the VCO output signal by time-varying values. This may effectively allow the VCO to output signals whose frequencies may be non-integer multiples of the reference signal.
This type of PLL may be utilized in a wireless communication device with various transmitters and receivers. The circuitry that handles the radio frequency signals, including the frequency divider, should be adapted to handle high frequencies of operation.